BxBFFT vs Altera Parallel FFT
BxBFFT vs Altera Parallel FFT
This page compares the BxBFFT vs the Altera Parallel FFT using data from Agilex7 implementations. This is also representative of other Altera FPGA families. For exact numbers in specific FPGAs, contact BxB.
The BxBFFT surpasses the Altera Parallel FFT in achievable Fmax, supported sizes, supported parallelism, supported features and supported controls. In particular, the Altera Parallel FFT doesn't currently have a bit reverse. Thus comparisons made here are made with the BxBFFT bit reverse turned off.
For 2-complex-point-per-clock parallelism (PPC2), the Altera Parallel FFT does better than the BxBFFT in all FPGA resource categories, but not in achievable Fmax.
For all other levels of parallelism (PPC>2), the BxBFFT surpasses the Altera Parallel FFT in Fmax, power consumption, ALM usage, and DSP usage. REG usage is about even. The Altera Parallel FFT is lower in M20K usage.
This summary is backed up by the data that is discussed below.
The Altera Parallel FFT only supports complex-to-complex power-of-2 FFTs with SSR also a power of 2. Below is a table showing which Altera Parallel FFTs synthesize, in the range from 128 point to 262144 point and PPC2 to PPC64.
Note that for the BxBFFT, all the boxes on the table below synthesize properly, and many more sizes in between. The BxBFFT supports all FFT sizes that are a multiple of powers of 2, 3, 5, and 7. The BxBFFT also supports all values of PPC that evenly divide into the FFT size.
Because the Altera Parallel FFT doesn't support the full range of tested sizes, the graphs below are missing some points for the Altera Parallel FFT. For the missing points, the Altera Parallel FFT simply doesn't work.
It's particularly important that the Altera Parallel FFT doesn't support PPC64 and doesn't support real-to-complex operation. These are needed to accept data directly from Altera's latest Agilex9 FPGAs with their built-in 64Gsps ADCs.
The plots below compare Fmax and setup Fmax estimated by Quartus. The X-Axis of the plot is divided into 6 sections, from PPC2 to PPC64. In each section, FFT size varies from 128 to 262144. This allows a single plot to show a wide overview of FFT performance across a range of FFT Sizes and PPCs.
The BxBFFT has pipelining controls, that can increase pipelining in targeted areas to meet timing. Graphs of the BxBFFT with very large pipelining are included below, showing the extra pipelining provides some limited improvement for high PPC. With or without this, Fmax performance is significantly higher than the Altera Parallel FFT.
The plot of restricted Fmax above takes into account both setup limitations and internal speed limitations of the DSPs and M20Ks. Currently the BxBFFT doesn't use the DSPs in way to attain their highest speeds, which imposes a limit on BxBFFT performance. The Altera Parallel FFTs use the DSPs in a better fashion, for a higher Fmax limit.
The plot of Setup-Limited Fmax above shows the speed limit when only setup time is taken into account. The setup-time limit is especially important because it is affected by FPGA placement and routing. Having a higher Setup-Limited Fmax means there is more timing margin, so high speeds can be maintained with more resilience against resource contention from other IP in the FPGA.
The conclusion from these two plots is that the Altera Parallel FFT can currently obtain higher speeds, but if the desired speed is below its limits the BxBFFT is more likely to keep that speed and close timing in a real design with significant resource contention.
The plot below compares power consumption estimated by Vivado for the BxBFFT vs power consumption estimated by Vivado for the AMD/Xilinx XFFT.
This shows that power consumption of an Altera Parallel FFT is as much as 5% lower than a BxBFFT for PPC2 but 5% or more higher for PPC>2. Overall this is a benefit for BxBFFT designs, since power consumption is more critical in larger designs where the BxBFFT does better.
The plot below compares ALMs measured by Quartus for the Altera Parallel FFT vs the BxBFFT.
The Altera Parallel FFT uses ~10% less ALMs than the BxBFFT for PPC2, but uses ~20% more ALMs when PPC>2. Overall this is a benefit for BxBFFT designs, since ALM usage is more critical in larger designs where the BxBFFT does better.
The plot below compares REGs measured by Quartus for the Altera Parallel FFT vs the BxBFFT.
The Altera Parallel FFT uses fewer REGs than the BxBFFT for PPC2. For PPC>2, neither has a clear advantage.
The plot below compares DSPs measured by Quartus for the Altera Parallel FFT vs the BxBFFT.
The Altera Parallel FFT is ~10% lower in DSP usage than the BxBFFT for PPC2. The Altera Parallel FFT is ~30% higher in DSP usage than the BxBFFT when PPC>2.
The plot below compares M20Ks measured byQuartus for the Altera Parallel FFT vs the BxBFFT. M20Ks are the one area where the Altera Parallel FFT does particularly well.
As can be seen, the Altera Parallel FFT is lower than the BxBFFT on M20Ks in essentially all cases. A typical difference is 30 M20Ks. To put this in perspective, it's not uncommon for an FPGA to have 10,000 M20Ks. So the amount of difference isn't large compared to the M20K resources on a chip.
The Altera Parallel FFT has parameters for FFT Size, PPC, forward/inverse FFT, bit-reversed in vs bit-reversed out, the setting of an amplitude shift schedule, and bit widths. The BxBFFT has all of these settings. For the BxBFFT, code is different for each FFT Size and PPC, where for the Altera Parallel FFT the same code is used with different parameter settings.
The Altera Parallel FFT has parameters to set floating point operation. The BxBFFT doesn't support floating point operation (for good reason).
The Altera Parallel FFT a parameter to create a global enable signal. The BxBFFT doesn't have a global enable. This would only be useful for reverse flow control, which the BxBFFT doesn't support.
The BxBFFT supports a number of features that the Altera Parallel FFT doesnt' support. These include options for a bit reverse, for real-to-complex FFTs, and for non-power-of-2 FFTs.
The BxBFFT also supports many controls that the Altera Parallle FFT doesn't support. These include pipelining controls, memory type controls, controls for monitoring amplitude within the FFT, controls for specifically setting the amplitude shift schedule, controls for setting the zero-point of input and output data, controls for splitting an FFT into multiple smaller FFTs, and controls for on-the-fly generation of twiddles.
The BxBFFT supports many more features than the Altera Parallel FFT, and especially the BxBFFT supports the most important features in which the Altera Parallel FFT is lacking. Where the two have features in common, the BxBFFT generally has finer control. Thus the BxBFFT can be more effective than the AMD/Xilinx XFFT in meeting algorithmic and implementation goals.
The BxBFFT is clearly a more useful FFT than the Altera Parallel FFT. In a comparison of resources, power, and speed, the BxBFFT comes out on top not because it is always better, but because it is better where the difference is more important.
However, what really sets the BxBFFT above the Altera Parallel FFT is the supported FFT Sizes, supported PPCs, supported features, and supported controls.
In particular a real-to-complex FFT at PPC 64 is important, because it can reduce a 64Gsps data stream to a 512MHz FPGA clock rate for processing of raw ADC data in an Agilex9. The Altera Parallel FFT can't do real-to-complex FFTs and can't do PPC64. The BxBFFT can do this, and can even do PPC128 for when the BxBFFT is used inside a 2x oversampling Polyphase Filter Bank.