BxBFFT Interfaces
The BxBFFT supports two different I/O interfaces. The first is a
BxB-custom interface. This interface allows control over advanced
reset options, and has parameters to set the timing relationship
between control signals and data. The second is a standard AXI-S
interface. A few customization options differ between the two
interfaces. When options are different, it is noted below.
BxBFFT Customization Parameters
The BxBFFT has several types of customization parameters that fit it
to almost any high-speed application. The first type of parameters is
those that must be set at delivery time.
Delivery-Time Parameters
These parameters must be chosen on delivery because they are highly
related to performance optimizations, and thus selecting them at
delivery time means that those optimizations can be applied to
provide the highest BxBFFT performance. Changing these options
requires a new delivery. These are the delivery-time parameters:
1. FFT_SIZE
This is often a power of 2, since power-of-2 FFTs have become
customary, they are simpler, and they are often slightly more
efficient. However, the BxBFFT supports additional sizes -- any
size that is a multiple of powers of 2, 3, 5, and 7. For
example, a 7000-channel BxBFFT is supported.
2. Real-to-Complex or Complex-to-Complex
BxBFFTs can process real input samples or complex input samples,
and this parameter selects which type of channelizer it is.
Real samples are convenient if the data is coming directly from
an ADC. In this case, selecting a real-to-complex BxBFFT avoids
the distortion of a separate real-to-complex filter that is
included in some designs. Complex samples may be the input if
the channelization is later in the processing, or if the ADC
performs complex sampling with inphase and quadrature
components. Output data samples are always complex. For
real-to-complex FFTs, the number of complex output points is
FFT_SIZE and the number of real input points is twice FFT_SIZE.
In all cases, the inverse FFT is also delivered.
3. Points per Clock (PPC)
BxBFFTs can process multiple input points simultaneously, so
that they can process ADC sampling rates that are higher than
the FPGA clock rate. PPC is a measurement of how many complex
input points are processed each clock. (If it is a
real-to-complex BxBFFT, the number of real input points
processed is twice this.) Note that in the literature PPC is
also sometimes called the SuperSample Rate (SSR) or the number
of phases. For a BxBFFT, PPC doesn't need to be a power of 2.
However, PPC must evenly divide into FFT_SIZE.
The next type of parameters are those that affect algorithmic
performance.
Amplitude Management Parameters
These parameters manage amplitudes within the FFT, which affect
numeric noise and the risk of overflow. They can be changed by
customers at compile time, after delivery. These are the amplitude
management parameters:
4. FFT Data Bits
The number of FFT Data Bits affects rounding error and the risk
of overflow that occurs inside each FFT stage of the BxBFFT. It
also affects speed and resources.
5. FFT Amplitude Management
There are multiple controls for management of FFT amplitude.
Mostly these are compile-time, although there are also controls
that can be enabled for run-time monitoring and control.
Amplitude must be controlled because if amplitudes are low,
there is excess rounding error in the FFT. If amplitudes are
high, there is too high a probability of overflow. The primary
difference between floating-point FFTs and fixed-point FFTs is
that for fixed-point FFTs, this amplitude control must be
performed to get good results. The primary benefit of floating
point is that this amplitude control is automatic. In most
practical applications, high FFT Data Bits can be selected and
limited amplitude control can be performed to give better
performance per watt in a fixed-point FFT than any floating
point implementation can achieve. One other problem with
amplitude management is that its control is often somewhat
arcane. The BxBFFT provides optional easier-to-use controls
that simply the problem immensely.
The next type of parameters are those that affect data formats.
I/O Parameters
These parameters affect the order and timing of data in/out of the
BxBFFT. These are the I/O parameters:
6. Input Bit Width
The number of Input Bits is only a parameter for a BxBFFT with
an AXI-S interface. For this case, setting the number of input
bits within the AXI-S word and the bit position within the word
allow a BxBFFT to directly interface with other AXI-S
components.
7. Output Bit Width
The number of Output Bits is often set to something less than
the number of FFT Data Bits, since additional FFT Data Bits are
often kept to reduce rouding error. If bits are removed, there
is a parameter controlling their placement in the output word.
This parameter is only available for BxBFFTs with AXI-S
interfaces.
8. Input and Output Data Order
Data order can be set to Fully Natural Order, Partially
Natural Order, or Scrambled Order. Usually Fully Natural Order
is selected, in which the first PPC samples are all on the same
clock. Partially Natural Order has the first sample on each
clock matching the clock number of the output. The second
sample matches the clock number plus the total number of clocks.
Selection of Input and Output data orders determines whether the
BxBFFT is implemented as Decimation-in-Time or
Decimation-in-Frequency, to match the requested orders. It also
selects the addition of buffers and bit-reverse-type modules.
9. Input and Output Zero Location and Nyquist Zone
There are controls to select whether data comes out with zero
location at the start, middle, or end. Zero at the end is
useful if an ADC is operating in the 2nd or 4th Nyquist Zone, in
which case the data is flipped. Zero at the end order flips it
back. For complex BxBFFTs only, the data order can put zero
frequency in the center. This is useful for taking the FFT of
complex baseband signals.
10. Forward Flow Control Enable
Flow control can always be controlled between vectors. Enabling
this parameter also allows a valid flag on data at each clock.
If this requires an extra input buffer it is added, but in most
circumstances an input buffer is already present and it is
shared. Note that for the BxBFFT flow control is not a signal
that halts the entire BxBFFT. Once all data for a particular
FFT has been accepted by the BxBFFT, that FFT proceeds without
interruption.
11. Sync and Valid Input and Output timing
This is for the BxB-custom interface only. For it, sync and
valid signals can be configured to precede or follow the data by
a desired amount. So for example, the sync signal that starts
an FFT could be on the same clock as the first data sample, or
it could preceded it by a specified number of clocks. The same
with the valid signal, if flow control is enabled. Timing can
be set separately for input and output.
12. Number of additional sideband signals
The BxB-custom interface allows additional sync signals to be
passed along with the FFT data, and kept aligned with it. The
AXI-S interface allows the same with TID and TDEST signals.
The next type of parameters are those that pipelining of the implementation.
Pipelining Parameters
Pipelining parameters have no effect on the output data values,
except for the delay in producing them. Instead, these parameters
add pipelining registers to help the BxBFFT meet timing. Changing
these parameters is primarily useful in designs with high resource
contention. These are the pipelining parameters:
13. Pipelining Default
This is a global control that selects default values for all
pipelining controls that aren't individually overridden.
14. Individual Pipelining Controls
There are many individual pipelining controls, the number of
which varies with the channelizer type and the number of
channels. There are pipeline controls both for the BxBFFT
filter and for individual stages of the BxBFFT FFT.
Memory Parameters
Memory parameters have no effect on the output data values, except
for the delay in producing them. Instead, these parameters select
which types of memory to use in various places within the BxBFFT.
Selections can be made between distributed memory and block memory.
In some cases, selections can be made between the different types of
block memory. In addition, for FFT twiddle stages the twiddle
generation can be pushed into an on-the-fly calculation circuit,
which eliminates almost all of the memory usage from that twiddle
stage. These are the memory parameters:
15. Block Memory Desirability in Percent
Normally small memories are fit into distributed RAM and large
memories are fit into block RAM. This desirability percentage
changes the calculation to encourage or discourage placement of
memories in block RAM. There are multiple controls for this,
including a global default and settings for the
FFT front-end I/O and each FFT stage.
16. Twiddle Source
For each FFT stage, the FFT twiddles can be selected to be
automatically generated instead of stored in a table. The
on-the-fly generator uses extra fabric resources and DSPs, but
can save significant memory resources.
17. FFT I/O Memory Forcing
There are controls to force a specific percentage of FFT I/O
memory into block RAM. These are seldom used; their purpose is
for designs that are exceeding 100% memory utilization to be
able to shift I/O memory utilization between memory types by
finely controlled amounts to make the design close.
Multi-Vector Parameters
By disabling a final radix-2 stage, a BxBFFT of size FFT_SIZE can be broken into
multiple smaller FFTs. This is rarely useful, but in certain situations can
provide higher efficiency for multiple simultaneous FFTs or provide FFT size flexibility.
The Multi-Vector parameters are these:
18. Number of Stages Enabled
The number of enabled stages can be reduced statically or it
can be set to be changed at run time. When final FFT stages
are omitted and the product of their radices is R, this turns a
BxBFFT of size FFT_SIZE into R FFTs of size FFT_SIZE/R. These
smaller FFTs share twiddle tables, and thus can be more efficient.
A downside is that data ordering can be more complex.
A Deeper Dive
If you want to know exactly what a BxBFFT interface looks like, here
are two System Verilog RTL templates that instantiate a 4096-point
BxBFFT at PPC4 with default values. These templates also include a
short test of the BxBFFT.
BxBFFT_4096_4_complex_BxBIF_template.sv
BxBFFT_4096_4_complex_BxBIF_template.sv
If you are using the AMD/Xilinx IP Integrator, an example of
configuring the BxBFFT through it is included on the page linked
below, at the bottom. This shows the BxBFFT IP Integrator
interface, and how well-organized it is in comparison with the
AMD/Xilinx XFFT:
Comparison of the BxBFFT with the
AMD/Xilinx XFFT.
Conclusions
Configuring the BxBFFT has been made as simple as possible, while
keeping the power to perform a very wide range of desirable
customizations.
No other comparable FFT offers such a wide range of features and
customizations.
The configuration process gives expert-level control without the
expert-level cost.
Links
BxBFFT Customization Deep Dive